Aleksey Danilov
Angestellt, RTL Engineer, Sequans Communications
Paris, Frankreich
Werdegang
Berufserfahrung von Aleksey Danilov
Bis heute 4 Jahre und 8 Monate, seit Nov. 2019
RTL Engineer
Sequans Communications
3 Jahre und 5 Monate, Juli 2016 - Nov. 2019
Engineer
Waviot
Developing of detection and demodulation algorithms for multi-channel ultra-narrow band receiver and their implementation in FPGA
Developing Matlab model and FPGA based implementation of digital pre-distorter algorithm for GSM and LTE RBS on Xilinx Virtex 7 chip
2 Jahre und 8 Monate, Dez. 2010 - Juli 2013
FPGA Engineer
Tecom group
VHDL code based FPGA design of video processing algorithms for digital TV test and measurement equipment in Altera Quartus II environment. Simulation Questasim/ModelSim. Debugging with Altera SignalTap. Experience with Altera IP Core DDR2 HPC. Timing constraints description using SDC format Implementation of digital quadrature demodulator for digitized composite analog video demodulation Models simulation using Matlab. Expereince with Agilent logic analyzer
11 Monate, Feb. 2010 - Dez. 2010
Software tester
MERA
Testing SS7 protocol stack software. Writing and execution Tcl-based automated testing scripts.
Ausbildung von Aleksey Danilov
Bis heute 13 Jahre und 9 Monate, seit Okt. 2010
Radio Engineering
Nizhniy Novgorod State Technical University named after R.Y. Alekseev (NSTU)
Field of research "Signal space-time processing in MIMO systems, relaying systems and wireless cooperative systems"
1 Jahr und 10 Monate, Sep. 2008 - Juni 2010
Radio Engineering
Nizhniy Novgorod State Technical University named after R.Y. Alekseev (NSTU)
DSP systems in communictions, radiolocation and control
3 Jahre und 10 Monate, Sep. 2004 - Juni 2008
Radio Engineering
Nizhniy Novgorod State Technical University named after R.Y. Alekseev (NSTU)
Signal generation and processing in radio systems
Sprachen
Englisch
Gut
Russisch
Muttersprache