Amit Mittal

Providing consulting to companies on different aspects of ASIC/SOC/FPGA/IP design/architecture and methodologies. -> Working on ASIC project in storage domain. I am responsible for architecture of Denali's DDR3 memory controller's integration in the ASIC. Frequency target is 400 MHz and protocol used is AXI. I am coming up with the requirements to integrate the controller to meet ASIC requirements on AXI side as well as on Phy side. -> I was responsible for specification, architecture, RTL, Linting, synthe

Being part of Sasken IP team, I was responsible for system level architecture of AHB2AXI and AXI2AHB bridges. My additional responsibilities included mentoring junior engineers on all design aspects and help them in module level architecture and reviewing their work. Simultaneously, I was responsible for synthesis setup for same design using RTL compiler tool.

Worked on latest low power methodologies using power gating and RTL compiler tool. Was responsible for design changes for low power methodology for DVFS. Did architecture and design of multi-layer AHB bus matrix from specification. Worked on Low power kit in the R & D team. To define the methodologies for the next generation designs and for low power changes.

Worked on Wimax (IEEE standard 802.16e) chipset (subscriber and base station) Accomplishments: • Schedule planning, system setup, team assignments, resource allocation, schedule tracking, and cross-site and cross-team communication for gatesim. • Designed the host controller for Nokia serial interface, ported on FPGA, debugged on board. • Made Phy layer test plan, executed and architected/designed one of the blocks. • Did initial synthesis of ASIC using Magma tools • Designed and verified one of the 6 FPGA

Worked on north bridge chipset (known as memory controller hub, MCH) for mobile platform Accomplishments: • Cross-team communication for specification, requirements, task and responsibilities scheduling, test plan ownership on PCI-express and mentoring team on various prospects. • System setup for PCI-express which had challenges of new design and combining two different PCIE modules. • Full chip and block level system setup for India site. • Training ownership for FE team members for architecture, verifica

Worked with Custom IC design team on Analog/Mixed Signal design tool Analog Design Environment which integrates other cadence tools like spectra, spectraVerilog simulators, and Monte Carlo etc. knowledge about HSPICE also, developed tests for ADE on open access database and suggested changes after getting full understanding of tool, worked on RCS and wrote fully automated tests.

Worked with SDH team in C-Dot as an Intern and implemented the pointer interpreter used in the STM-1 (Synchronous Transport Module-1) frame, a part of the SDH (Synchronous Digital Hierarchy), using VHDL, Implement frame detector for STM1 frame and counter to count the number of frames. Got pretty good understanding of SDH technology, finished three different projects in two months under tight time line, worked closely with research engineers and learnt good structured flow of defining, solving and implement

Microelectronics