SaratChandra Mandapati

FPGA Programming

The thesis task involved implementation of CAN controller protocol on FPGA (Verilog),implementation of transceiver add-on board using Eagle CAD, implementation of Nios ii embedded processor using Altera system build tools and programming Nios ii processor.

Designing Driver code for LCD display in VHDL, for Xilinx Vertex 5 board

I was the Lab assistant in Digital design Lab For Master Students. Tools used: Xilinx ISE, Plan Ahead, EDK.

Implementing and testing RSA cryptography algorithm on Xilinx Spartan 3E FPGA board.

Designing websites for state government.

Digital designing using VHDL,VLSI technology.